In a computer system with selective power control, individual memory banks that are not in current use may be placed in a reduced power state to save electrical power and extend battery life. Such implementations may wait until a need for a particular bank of memory arises before powering up that bank. Since transitioning from a reduced power state to a fully operational state takes a finite period of time, the system may have to wait for the needed bank of memory to be powered up and ready before accessing that bank of memory. This may force the processor or other accessing device to wait until the memory bank is ready, thus delaying the affected operations.